1. Field of the Invention
The present invention relates to a digital lock detector and a frequency synchronizer using the same, and more particularly, to a digital lock detector capable of detecting whether or not a frequency outputted from a phase locked loop (hereinafter, referred to as ‘PLL’) is locked, and a frequency synthesizer using the same.
2. Description of the Related Art
Typically, charge pump PLLs have been widely used in designing radio frequency (RF) synthesizers for multi-band mobile communications. Analog circuits designing technology is integrated in such charge pump PLLs.
Thus, it is difficult to integrate a charge pump PLL with a digital baseband-signal processing block because of the characteristics of analog circuits and analog signals in which a separate analog/RF library needs to be added to a design library provided in a standard digital complementary metal-oxide-semiconductor (CMOS) process. However, with the recent development of process techniques, digital baseband-signal processing blocks are under development using nanoscale digital CMOS processes.
A frequency synthesizer using a digital PLL, according to the related art, is unsuited to a local oscillator demanding high-quality phase noise, due to its high phase noise and jitter noise. Recently, all-digital PLLs (ADPLLs) that are achieved by applying digital PLL techniques to frequency synthesizers for mobile communications have been developed and used.
An ADPLL utilizes a digitally controlled oscillator (DCO), which may be realized using an LC resonator. Thus, the ADPLL has superior characteristics regarding phase noise and jitter noise.
Therefore, studies on digital lock detectors are ongoing in order to detect the lock condition of a digital PLL in a quick and accurate manner.